Routing for analog chip designs at NXP Semiconductors
Publication date
2011-01-24
Authors
van den Akker, Marjan
Beelen, T.
Bisseling, Rob h.
Auer, B. O Fagginger
von Heymann, F.
Müller, T.
Rommes, J.
Editors
Planqué, Bob
Bhulai, Sandjai
Hulshof, Joost
Kager, Wouter
Rot, Thomas
Advisors
Supervisors
DOI
Document Type
Part of book
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Abstract
During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP. This resulted in an heuristic approach, which we presented at the end of the week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach.
Keywords
Wiskunde en Informatica (WIIN), Mathematics, Wiskunde en computerwetenschappen, Landbouwwetenschappen, Wiskunde: algemeen
Citation
van den Akker, J M, Beelen, T, Bisseling, R H, Fagginger Auer, B O, von Heymann, F, Müller, T & Rommes, J 2011, Routing for analog chip designs at NXP Semiconductors. in B Planqué, S Bhulai, J Hulshof, W Kager & T Rot (eds), Proceedings of the 79th European Study Group Mathematics with Industry. VU University Amsterdam, pp. 117-131.